A 54 Mbps ( 3 , 6 ) - Regular Fpga Ldpc Decoder
نویسنده
چکیده
Applying a joint code and decoder design methodology, we develop a high-speed (3, k)-regular LDPC code partly parallel decoder architecture, based on which a 9216-bit, rate1/2 (3, 6)-regular LDPC code decoder is implemented on Xilinx FPGA device. When performing maximum 18 iterations for each code block decoding, this partly parallel decoder supports a maximum symbol throughput of 54 Mbps and achieves BER 10−6 at 2dB over AWGN channel.
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